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| HD74LVC1G57 Configurable Multiple-Function Gate REJ03D0011-0300Z Rev.3.00 Jun. 29, 2004 Description The HD74LVC1G57 has configurable multiple-function gate in a 6-pin package. The Output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, NAND, NOR, EX-NOR. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features * The basic gate function is lined up as renesas uni logic series. * Supply voltage range: 1.65 to 5.5 V Operating temperature range: -40 to +85C * All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) * Output current: 4 mA (@VCC = 1.65 V) 8 mA (@VCC = 2.3 V) 24 mA (@VCC = 3.0 V) 32 mA (@VCC = 4.5 V) * All the logical input has hysteresis voltage for the slow transition. * Ordering Information Part Name HD74LVC1G57CPE HD74LVC1G57CLE Package Type WCSP-6 pin Package Code TBS-6V TBS-6AV CP CL Package Abbreviation Taping Abbreviation (Quantity) E (3,000 pcs/reel) Article Indication Marking Year code Month code KRYM Rev.3.00 Jun. 29, 2004 page 1 of 1 HD74LVC1G57 Function Table Inputs IN2 L L L L H H H H H: High level L: Low level L L H H L L H H IN1 L H L H L H L H IN0 H L H L L L H H Output Y Pin Arrangement 0.9 mm Height 0.5 mm 0.5 mm pitch 0.17 mm 6-Ball (CP) IN0 0.23 mm 6-Ball (CL) 3 4 Y GND 2 5 VCC 1.4 mm Pin#1 INDEX IN1 1 6 IN2 (Bottom view) (Top view) Logic Diagram IN0 Y IN1 IN2 Rev.3.00 Jun. 29, 2004 page 2 of 9 HD74LVC1G57 Function Selection Table Logic Function 2-input AND 2-input AND with both inputs inverted 2-input NAND with one input inverted 2-input OR with one input inverted 2-input NOR 2-input NOR with both inputs inverted 2-input EX-NOR 1 4 2, 3 2, 3 4 1 5 Figure No. Logic Configurations VCC VCC A B A B Y Y A 1 (IN1) (IN2) 6 B A B Y A B Y Y A 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y Figure 1. 2-inputs AND Gate VCC Figure 2. 2-inputs NAND Gate with A input inverted VCC A B A B 1 (IN1) (IN2) 6 Y 2 (GND) (VCC) 5 B A B A B 1 (IN1) (IN2) 6 B Y 2 (GND) (VCC) 5 Y A 3 (IN0) (Y) 4 Y Y A 3 (IN0) (Y) 4 Y Figure 3. 2-inputs NAND Gate with B input inverted VCC Figure 4. 2-inputs NOR Gate A A B Y 1 (IN1) (IN2) 6 B 2 (GND) (VCC) 5 3 (IN0) (Y) 4 Y Figure 5. 2-inputs EX-NOR Gate Rev.3.00 Jun. 29, 2004 page 3 of 9 HD74LVC1G57 Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Symbol VCC VI VO IIK IOK IO ICC or IGND ja Tstg -0.5 to 6.5 -0.5 to 6.5 Ratings V V V Unit Test Conditions Output voltage range *1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Package Thermal impedance Storage temperature Notes: -0.5 to VCC + 0.5 -0.5 to 6.5 -50 -50 50 100 143 123 -65 to 150 Output : H or L VCC : OFF VI < 0 VO < 0 VO = 0 to VCC mA mA mA mA C/W C CP CL The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOL 0 0 -- -- -- -- -- IOH -- -- -- -- -- Input transition rise or fall rate t / v 0 0 0 Operating free-air temperature Ta -40 Note: Unused or floating inputs must be held high or low. Min 1.65 5.5 5.5 VCC 4 8 16 24 32 -4 -8 -16 -24 -32 20 10 5 85 C ns / V VCC = 4.5 V VCC = 1.65 to 1.95 V, 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 4.5 V VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V Max V V V mA VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V Unit Conditions Rev.3.00 Jun. 29, 2004 page 4 of 9 HD74LVC1G57 Electrical Characteristics Ta = -40 to 85C Item Threshold voltage Symbol VT + VCC (V) 1.8 2.5 3.3 5.0 0.8 1.2 1.6 2.3 0.4 0.6 0.9 1.5 0.4 0.4 0.4 0.4 Min Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.5 1.4 1.7 2.3 3.0 0.7 1.0 1.4 2.0 0.7 0.8 0.9 1.0 -- -- -- -- -- -- 0.1 0.45 0.3 0.4 0.55 0.55 5 10 500 10 -- Max Unit V Test condition VT- 1.8 2.5 3.3 5.0 VT 1.8 2.5 3.3 5.0 Output voltage VOH 1.65 to 5.5 1.65 2.3 3.0 4.5 VCC-0.1 1.2 1.9 2.4 2.3 3.8 -- -- -- -- -- -- -- -- -- -- V IOH = -100 A IOH = -4 mA IOH = -8 mA IOH = -16 mA IOH = -24 mA IOH = -32 mA IOL = 100 A IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA IOL = 32 mA VOL 1.65 to 5.5 1.65 2.3 3.0 4.5 Input current Quiescent supply current IIN ICC ICC 0 to 5.5 5.5 3 to 5.5 0 3.3 A A VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 One input at VCC-0.6 V, Other input at VCC or GND Output leakage current Input capacitance IOFF CIN A pF VIN or VO = 0 to 5.5 V VIN = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00 Jun. 29, 2004 page 5 of 9 HD74LVC1G57 Switching Characteristics VCC = 1.8 0.15 V Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL 3.2 Min Max 14.4 ns Unit Test Conditions CL = 30 pF, RL = 1.0 k IN FROM (Input) Y TO (Output) VCC = 2.5 0.2 V Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL 2.0 Min 8.3 Max ns Unit Test Conditions CL = 30 pF, RL = 500 IN FROM (Input) Y TO (Output) VCC = 3.3 0.3 V Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL 1.5 Min 6.3 Max ns Unit Test Conditions CL = 50 pF, RL = 500 IN FROM (Input) Y TO (Output) VCC = 5.0 0.5 V Ta = -40 to 85C Item Propagation delay time Symbol tPLH tPHL 1.1 Min 5.1 Max ns Unit Test Conditions CL = 50 pF, RL = 500 IN FROM (Input) Y TO (Output) Operating Characteristics Ta = 25C Item Power dissipation capacitance Symbol CPD VCC (V) 1.8 2.5 3.3 5.0 -- -- -- -- Min 20 20 21 22 Typ -- -- -- -- Max Unit pF Test Conditions f = 10 MHz Test Circuit Measurement point From Output CL * RL Note: CL includes probe and jig capacitance. Rev.3.00 Jun. 29, 2004 page 6 of 9 HD74LVC1G57 * Waveforms tr tf 90% Input Vref 10% t PLH 90% Vref 10% t PHL VI GND VOH In phase output Vref Vref VOL VOH Out of phase output t PHL Vref Vref VOL t PLH VCC (V) VI 1.80.15 2.50.2 3.30.3 5.00.5 INPUTS tr / tf 2 ns 2 ns Vref VCC / 2 VCC / 2 1.5 V VCC / 2 CL 30 pF 30 pF 50 pF 50 pF RL 1.0 k 500 500 500 VCC VCC 3 V 2.5 ns VCC 2.5 ns Notes: 1. Input waveform : PRR 10 MHz, Zo = 50 . 2. The output are measured one at a time with one transition per measurement. Rev.3.00 Jun. 29, 2004 page 7 of 9 HD74LVC1G57 Package Dimensions TBS-6V EIAJ Package Code JEDEC Code Mass (g) 0.001 Lead Material D ZD e C B E B A Pin #1 index area // y1 C 1 C 2 6xb x M C A B x M C e ZE C Seating plane Symbol A1 A2 yC A A1 A2 b D E e x y y1 ZD ZE Dimension in Millimeters Min Typ Max 0.50 0.10 0.15 0.35 0.19 0.15 0.17 0.90 1.40 0.50 0.05 0.05 0.20 0.20 0.20 Rev.3.00 Jun. 29, 2004 page 8 of 9 A HD74LVC1G57 TBS-6AV EIAJ Package Code JEDEC Code Mass (g) 0.001 Lead Material D ZD e C B E B A Pin #1 index area // y1 C 1 C 2 6xb x M C A B x M C e ZE C Seating plane Symbol A1 A2 yC *Reference value. A A1 A2 b D E e x y y1 ZD ZE Dimension in Millimeters Min Nom Max 0.50 0.155 0.185 (0.315)* 0.25 0.20 0.90 1.40 0.50 0.05 0.05 0.20 0.20 0.20 Rev.3.00 Jun. 29, 2004 page 9 of 9 A Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0 |
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